1. Field of the Invention
The present invention relates to a high breakdown voltage semiconductor device and a fabrication method thereof. More particularly, the present invention relates to a high breakdown voltage MOS (Metal Oxide Semiconductor) transistor which achieves a high breakdown voltage while particularly suppressing an increase in on-resistance to the extent possible.
2. Description of the Related Art
For isolation of elements on a semiconductor device, a junction isolation technique using pn junction has been conventionally commonly used. However, in recent years, dielectric isolation has been used which is a technique of forming a trench in an SOI (Silicon On Insulator) substrate having a buried insulating film, the trench reaching from an SOI substrate surface to the buried insulating film, and forming an insulating film inside the trench.
Such SOI-trench isolation is particularly effective for high breakdown voltage power type semiconductor devices, which generally require formation of deep isolation. This is because, in the high breakdown voltage power type semiconductor, although the area of an isolation region disadvantageously becomes large when the pn junction isolation is used, use of the SOI-trench isolation makes it possible to reduce the area of the isolation region. As a result, it is possible to miniaturize a chip. In addition, advantageously, crosstalk between elements is eliminated, so that a plurality of high breakdown voltage power elements (output section) and a plurality of low breakdown voltage elements (drive circuit portion for the output section) can be readily formed on the same chip.
Due to advantages as described above, the high breakdown voltage power element formed on an SOI substrate has attracted attention.
In general, the performance of the high breakdown voltage power element is indicated by the breakdown voltage and the on-resistance. However, there is typically a trade-off therebetween, i.e., it is difficult to simultaneously achieve a high breakdown voltage and a low on-resistance. Therefore, attempts have been made for many years to do so. Particularly, in recent years, a high breakdown voltage power semiconductor product employing an SOI substrate has been mass-produced, and a high-breakdown voltage and low-on-resistance high breakdown voltage power element formed on an SOI substrate has been vigorously developed.
An exemplary conventional high breakdown voltage MOS transistor is illustrated in FIG. 10. This is a technique described in JP 2004-096083 A (particularly, claim 1 and FIG. 1), particularly relating to a high breakdown voltage P-channel MOS transistor. A practical example of such a high breakdown voltage P-channel MOS transistor is a driver IC for a PDP (plasma display panel) illustrated in FIG. 11. HP1 to HP3 of FIG. 11 each correspond to the high breakdown voltage P-channel MOS transistor of FIG. 10. This IC is characterized in that a high voltage (VDDH: one hundred and several tens of voltages) is applied to a gate of the high breakdown voltage P-channel MOS transistor. Therefore, it is necessary to increase a gate oxide film thickness so as to secure a sufficient dielectric breakdown voltage. Therefore, the structure of FIG. 10 also employs a thick gate oxide film.
Hereinafter, as one example of the conventional high breakdown voltage semiconductor device of FIG. 10, a high breakdown voltage P-channel MOS transistor will be described.
This P-channel MOS transistor includes an SOI substrate composed of an N- or P-type support substrate 11, a buried oxide film 12, and an N-type active layer 13, as illustrated in FIG. 10.
A P-type drain offset region 14 is formed on the N-type active layer 13 of the SOI substrate, and an N-type well region 15 is formed on the same N-type active layer 13 and at a location two-dimensionally apart from the P-type drain offset region 14.
A P-type source region 16 and an N-type body contact region 17 are formed on the N-type well region 15. Further, a P-type drain region 18 is formed on the P-type drain offset region 14.
A LOCOS oxide film 19 is formed on at least the P-type drain offset region 14, the N-type well region 15, a region of the N-type active layer 13 interposed between the P-type drain offset region 14 and the N-type well region 15, and the like.
A gate electrode 21 is formed via a thick gate oxide film 20 on the N-type well region 15. Note that the LOCOS oxide film 19 can double as the thick gate oxide film 20, and such a structure is illustrated in FIG. 10.
A source electrode is connected onto the P-type source region 16 and the N-type body contact region 17, and a drain electrode is connected onto the P-type drain region 18. A substrate electrode is connected to the N- or P-type substrate 11.
In order to measure an off breakdown voltage of such a P-channel MOS transistor, a negative potential is applied to the drain electrode and the substrate electrode while setting the source electrode and the gate electrode to be GND.
When an inverse bias voltage is applied between the drain and the source in this manner, the P-type drain offset region 14 and a portion of the N-type active layer 13 under the P-type drain offset region 14 are depleted. The voltage applied between the drain and the source is held by a depletion layer thus formed.
When the voltage applied between the drain and the source is increased to a certain voltage at which a field formed in the depletion layer reaches a critical field, avalanche breakdown suddenly occurs, so that a current starts flowing between the drain and the source. The voltage applied in this case is the breakdown voltage value of a transistor. Therefore, in order to increase the breakdown voltage, it is necessary to adjust an impurity concentration of the P-type drain offset region 14 (hereinafter, the term “concentration” may be used interchangeably with the term “impurity concentration”) so that the depletion layer sufficiently becomes spread, thereby relaxing a field intensity.